Front-end Engineer (Synthesis, LEC, Verification) Local to CA

Title: Front-end Engineer (Synthesis, LEC, Verification)

Location: Irvine CA (Must be local to CA)

Duration: 4 Months 

Responsibilities:

• Synthesis of blocks for high speed wired data communication chip, including DFT insertion
• Logic Equivalency Check for rtl to gate level netlist for complex arithmetic intensive datapath blocks.
• Static Timing Analysis for the blocks.
  Verification of RTL hardware implementations in Verilog/ SystemVerilog.
• Gate level Simulation.

 

Required skills/knowledge:

 

• 5 years plus experience in ASIC implementation
• Knowledge of Verilog HDL language and RTL coding.
• Must have extensive experience in Synthesis using Synopsys Design Compiler.
• Understanding and knowledge of synthesis and timing constraints.
• Experienced in doing Logic Equivalency (LEC), using Conformal LEC (Cadence).
• Functional verification

 

Preferred skills/knowledge:

 

• Power Analysis experience
• Working experience with Synopsys Tetramax DFT checks and MBIST implementation
• Working knowledge for Virage STAR memory compiler and MBIST hook up
• Experience in working with Arithmetic blocks
• Knowledge of Signal Processing concepts.

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Thanks & Regards

David. P. Desai
Sigma Analysts Inc
david@analystusa.com
http://www.linkedin.com/in/davidsigma
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